Double gated and tri-gated transistors have higher scalability than single gated FETs since the multiple gates help to control the potential in the body. Among the several double gated and tri-gated device architectures, the FINFET has been considered as one of the most promising candidates for 32 nm node technology and beyond because it combines the critical elements of superior scalability found in all multi gated devices with the manufacturability of conventional transistors.
The body of a FINFET device having a double gate or a tri-gate consists of a thin (on the order of about 10 nm) vertical crystalline semiconducting wall called a FIN which typically extends from a surface of an underlying substrate. In double gated FINFETs, gate material warps around both sides of the FIN creating a channel on each side thereof. For a tri-gate FINFET device, the gate material is located atop the FIN as well as around both sides of the FIN creating a channel on each side of the FIN as well as atop the FIN.
The main advantages of a FINFET structure over other multi-gated device designs is that the self-aligned gates can be fabricated using a single lithographic and etching step.
In a conventional FINFET gate design layout such as shown in FIG. 1B, large source/drain landing (i.e., contact pads) 12 are used to connect an array of narrow FINS 14 in parallel at two ends. In FIG. 1B, reference numeral 10 denotes the active area, while reference numeral 16 denotes the gate. For comparison, FIG. 1A shows a conventional design layout for a planar FET.
For FIG. 1A, the planar FET ground rule is equal to the contact-gate overlay which is the distance d1 between the source/drain contact pads 12 and the gates 16. In FIG. 1B, the FINFET ground rule is equal to the contact-gate overlay plus the contact-active overlay. The ground rule for the FINFET structure is thus represented by the distance d2. The particular design layout shown in FIG. 1B is, however, unsuitable for actual FINFET technology since the use of source/drain landing pads inevitably increases the gate contact pitch due to overlay requirements.
Moreover, and in a conventional FINFET design layout, the minimum spacing from the source/drain contact to the gate is the contact-to-gate overlay plus the contact-to-active overlay. This is undesirable since the layout efficiency of a FINFET is severely degraded over that of a conventional planar FET. Furthermore, the use of source/drain landing pads also complicates spacer etching of the small space between the FINFET gate and the landing pad.
In 32 nm node technology and beyond, the minimum pitch required for active layers will be reduced to approximately 120 nm or less. When such a small pitch is used, the source/drain contact formation becomes a serious challenge due to gate-to-active overlay requirements and the need for raised source/drain regions for series resistance reduction.
Elimination of source/drain landing pads simultaneously solves both of the above mentioned problems, but requires that parallel FINS be strapped together. One reported idea, which is described by J. A. Choi et al., IEDM, 2004, p. 647, is to strap the FINs together by local interconnects. This particular scheme is shown, for example, in FIG. 2. One problem with the scheme described by J. A. Choi et al. is that the addition of local interconnects significantly increases the parasitic capacitance, thus degrading the overall circuit performance.
In view of the above, there is a need for providing an alternative contact scheme for FINFET structures that include multiple FINs.